M12L2561616A-6TIG2A
DRAM 256Mb 16Mx16 166MHz TSOP54
M12L2561616A(2A).pdf
* JEDEC standard 3.3V power supply
* LVTTL compatible with multiplexed address
* Four banks operation
* MRS cycle with address key programs
- CAS Latency ( 2 & 3 )
- Burst Length ( 1, 2, 4, 8 & full page )
- Burst Type ( Sequential & Interleave )
* All inputs are sampled at the positive going edge of
the system clock
* Burst Read single write operation
* DQM for masking
* Auto & self refresh
* 64ms refresh period (8K cycle)
M12L2561616A(2A).pdf * JEDEC standard 3.3V power supply
* LVTTL compatible with multiplexed address
* Four banks operation
* MRS cycle with address key programs
- CAS Latency ( 2 & 3 )
- Burst Length ( 1, 2, 4, 8 & full page )
- Burst Type ( Sequential & Interleave )
* All inputs are sampled at the positive going edge of
the system clock
* Burst Read single write operation
* DQM for masking
* Auto & self refresh
* 64ms refresh period (8K cycle)