• Four independent DMA channels, each with separate reg-
isters for Mode Control, Current Address, Base Address,
Current Word Count and Base Word Count.
• Transfer modes: Block, Demand, Single Word, Cascade
• Independent autoinitialization of all channels
• Memory-to-memory transfers
• Memory block initialization
• Address increment or decrement
• Master system disable
• Enable/disable control of individual DMA requests
o Directly expandable to any number of channels
• End of Process input for terminating transfers
• Software DMA requests
• Independent polarity control for DR EQ and DACK signals
• Compressed timing option speeds transfers -up to 2M words/second
• +5 volt power supply
• Advanced N-channel silicon gate MOS technology
• 40 pin Hermetic DIP package
